Illustrated in FIG. 1 is a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100. For an n-type MOSFET, the transistor 100 includes n-type source and drain regions 120a, 120b, respectively, formed in a p-doped substrate 110. A gate electrode 130 is disposed between the source and drain regions 120a, 120b, this gate electrode being separated from the substrate 110 and the source and drain regions 120a–b by a gate insulating layer 140. Insulating layers 150a, 150b further isolate the gate electrode 130 from the surrounding structures. Conductors 160a, 160b (e.g., conductive traces) may be electrically coupled with the source and drain regions 120a, 120b, respectively. If a sufficient voltage is applied to the gate electrode—i.e., the “threshold voltage”—electrons will flow from the source to the drain, these mobile electrons concentrated in a thin “inversion layer” 170 extending between the source and drain regions 120a, 120b. Of course, those of ordinary skill in the art will recognize that the complementary MOSFET—i.e., the p-type MOSFET—will have a similar structure (p-type source and drain regions on an n-type substrate), and that a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit will utilize both n-type and p-type MOSFETs (or, more generally, both NMOS and PMOS devices).
In conventional MOSFET devices, the gate electrode 130 typically comprises a poly-silicon material, whereas the gate insulating layer comprises Silicon Dioxide (SiO2). To increase circuit density and improve device performance, it may be desirable to scale down the thickness of the gate insulating layer 140 (often referred to as the “gate oxide”). As the thickness of the gate oxide is scaled down, it may be necessary to use a material having a higher dielectric constant—i.e., a “high-k dielectric”—as the gate oxide in order to maintain sufficient capacitance while also preventing failure by electron tunneling. Integration of a poly-silicon gate electrode onto a high-k gate oxide has, however, proven difficult due to interactions between the poly-silicon gate material and the high-k insulating material. Furthermore, as the thickness of the gate insulating layer 140 is further scaled down (e.g., below about 20 Angstroms), it may be desirable to use an alternative material to poly-silicon as the gate electrode, in order to eliminate the thickness contribution of poly depletion to the gate oxide (i.e., to eliminate that portion of a poly-silicon gate electrode that becomes depleted of free charges and, hence, adds to the effective thickness of the gate insulating layer).
Use of a metal gate electrode can eliminate the above-described effects of depleted poly-silicon in the gate electrode, and a metal gate electrode may also enable further scaling down of the gate oxide thickness. However, use of metal materials as the gate electrode in NMOS and PMOS devices has also proven difficult. To optimize the performance of a transistor, the metal used at the gate electrode should be selected to provide a work function that will achieve a sufficiently low (but non-zero) threshold voltage for the transistor (e.g., 0.2 V to 0.3 V). Many metals have a suitable work function (a value representing an energy level of the most energetic electrons within the metal), but are thermally unstable at high temperature. Process flows for transistors can often reach temperatures of 900° C. and, therefore, during subsequent processes, the work function of these metals may shift to unsuitable values. Furthermore, at elevated temperatures, these metal gate materials may react with the gate insulating layer, thereby degrading its insulating properties. Other metals are thermally stable at the temperatures present in transistor process flows; however, these metals have work functions that are inadequate for high performance transistors.